Not Applicable
Not Applicable
1. Field of Invention
The present invention relates to electrical devices. More specifically, the present invention relates to electrically-programmable interconnect architectures without active devices, capable of making user-defined connections between conductors to form desired networks. Certain aspects of the present invention relate to general-purpose electrically-programmable interconnect architectures which form sequential electrical connections between a master terminal and each of a plurality of slave terminals; such architectures may find widespread utility in a variety of applications. Other aspects of the present invention relate to structures and architectures useful primarily for interconnecting circuits in stacked arrays, especially integrated circuits (ICs) contained within stacked, mating programmable packages such as those described in my related U.S. Pat. No. 5,838,060. In particular, the present invention provides the programmable interconnect architectures necessary for such packages to be built and programmed easily and economically, thereby providing a new, powerful method of flexibly combining arrays of user-selected ICs, housed within packages containing said architectures, so that the arrays of configured packages contain the entire system schematic within their programmed connections.
2. Description of Prior Art
It has long been realized that electrical circuits can achieve higher densities, greater modularity, and higher speeds when they are stacked together in a three-dimensional array, rather than spread out over a comparatively large area in a two-dimensional pattern. Different stacked arrangements or circuits have been utilized for many years; in fact, even before the advent of the integrated circuit (IC) chip, stacked modules, each containing several electrical components, were sometimes used as xe2x80x9cbuilding blocksxe2x80x9d in electrical systems designs. The most common use today of this circuit-stacking technique is the popular and powerful xe2x80x9cstacked PC-boardxe2x80x9d concept (where printed circuit boards (PC-boards) are plugged into an array of parallel receptacles or xe2x80x9cslotsxe2x80x9d in a motherboard). Almost all computers today take advantage of this useful arrangement.
This arrangement, as is currently used in personal computers, demonstrates the compactness and modularity of the stacking concept. A personal computer with several filled slots may have far more total PC-board area even than the footprint of the computer, and the add-on cards can be selected from thousands of available boards. However, since the stacking concept is used on a relatively large scale (stacked PC-boards populated with standard IC packages, each board as large as 10 cmxc3x9730 cm, separated by approximately 2 cm. between parallel boards), the circuit is still spread out over a large physical space; so the relative speed advantage inherent in a stacked arrangement is less apparent. In fact, in a standard personal computer today advertised to run at a given clock speed, at most only a small section of the motherboard actually runs at the specified speed; more commonly today, only a section of the CPU runs at the specified speed. In most personal computers today, the bus which connects the stacked PC-boards to the CPU runs much slower than the system clock speed; this speed ratio can be ten times or more. Clearly, although this stacked arrangement may in fact be somewhat faster than an equivalent but entirely two-dimensional arrangement, the inherent speed advantage of a stacked circuit arrangement is not apparent in this example case.
Yet stacked circuit arrangement at the PC-board level is by far the most prevalent application of the stacking concept today, in spite of the lack of significant speed advantages. This has come about for a variety of reasons, primarily having to do with cost and time-to-market. In order to understand why stacked PC-board applications are so overwhelmingly popular compared to other stacking methods, it is necessary to look at the methodology commonly used when building an electronic system.
ICs as they are produced today are inherently two-dimensional. They are produced by building up successive layers, each patterned using plate micro-photolithography, on a two-dimensional wafer substrate. Each wafer is subsequently diced into individual IC chips, each of which performs a required electrical function. IC chips are usually sold pre-packaged (in packages selected by the IC manufacturers) and pretested both at the wafer level and in packaged form. The packages used are generally made in technologies which bridge the microscopic world of the integrated circuit, where critical dimensions are currently measured in tenths of micrometers, to the macroscopic world of the PC-board, where critical dimensions are now measured in tenths of millimeters. Almost all chip packages are designed to be mounted directly onto a PC-board, so the package external contact points (pins, solder-bumps, etc.) are spaced at intervals compatible with PC-board dimensions. Because the external contact points are spread out compared to chip dimensions, most IC packages are significantly larger than their enclosed chip, yet smaller than a PC-board; yet since the design, substrate and fabrication costs per unit area are generally much less for package technologies than for IC technologies, the package cost is typically much less than the IC die cost. To make a system, designers connect different ICs together using PC-boards whose contacts and conductors are designed to mate with the external contact points of each IC package.
So when designing a new electronic system, systems designers can customize circuits at several levels. They can design new IC chips, custom packages, or custom PC-boards.
The costs and lead-time of developing a new IC are quite large, and are many times only justifiable where a large prospective market is anticipated for the new IC. Some custom ICs, also known as application-specific ICs (ASICs), use streamlined design techniques, to make a new IC design more cost-effective even for a smaller potential market; but these are still a relatively small sector of the total IC market. In general, systems designers use standard, relatively economical ICs as much as possible in their designs; customizing a particular system by designing new custom IC chips is almost never done.
Designing and building custom packages is also expensive, and the lead-time from the beginning of the package design cycle is quite long. Because of this, chip packages are generally considered as being relatively fixed, especially in terms of the package external form factor. Again, systems designers rely on standard packages as much as possible in their designs.
In contrast, building a new design using prior-art techniques always requires a custom PC-board design, in order to define the connectivity of the individual components and packaged chips, and thus define the entire circuit. The tooling costs and lead-times for custom PC-boards are both affordable, especially when compared with the costs of producing custom packages or ASICs for each chip in a design. Thus, as much as possible, systems designers use standard IC chips, in standard packages, mounted on custom PC-boards, in order to build their products.
With this currently prevalent methodology in mind, it is easy to see why circuit stacking is primarily used at the PC-board level. In any proposed stacking technology, a xe2x80x9cpancake stackxe2x80x9d of interconnected circuits requires that each xe2x80x9cpancakexe2x80x9d have its own custom interconnections, which mate with the connections on the pancakes above and below it in the stack. These custom interconnections now define the wiring connectivity of the components, and thus define the system. As discussed above, custom chips and custom packages are expensive and time-consuming to produce using standard techniques, while custom PC-boards are relatively cheaply and quickly fabricated; also, almost all systems today require custom PC-boards anyway. Thus, using prior-art technologies, relative cost and time-to-market dictate that circuit stacking be commonly used only at the PC-board level, despite the relatively low speed of this approach.
In the past, such speed considerations were not of paramount importance; systems were able to run at speeds consistent with the available integrated circuits using an essentially two-dimensional system-level arrangement. Today, however, integrated circuits are becoming fast enough that the interconnections between chips can dominate overall system performance. In recent years, different circuit stacking arrangements that are inherently faster have begun to be investigated.
The comparative speed advantages between different stacking schemes can be qualitatively compared by comparing the longest distance a signal might have to travel. This distance dictates the time-of-flight for a worst-case electrical signal; and the time-of-flight determines the delay between the time that the driving circuitry signals a condition and the time that the receiving circuitry first becomes aware of that condition and begins to formulate a response. This longest distance also gives an indication of the worst-case parasitic resistance, inductance and capacitance values in a given technology if the transmission-line properties of a given path are not matched well enough to allow clean transmission-line propagation to occur. Even when an attempt has been made to optimize the PC-board traces as strip transmission lines, the longest traces with the most connections are typically the worst performers of the system; even systems with optimized traces rarely are able to prevent reflections and other signal degradations when the transmission line splits.
And such parasitic values in turn determine much of the power consumption of the system. If transmission-line parameters are not optimized, these represent capacitances to be charged and inductances to overcome when signals are transmitted; and if the transmission-line parameters are optimized, they are still related to the time duration for which each signal should be held valid.
In the personal-computer example mentioned above, using perhaps eight stacked PC-boards with edge connectors at one end of one side, the worst-case signal would have to travel from the first board""s far end to its connector, then along the motherboard to the farthest board""s connector, and then out to the far end of that board. This would total perhaps 2 cm from an IC die through its package, about 30 cm along one end board, another 7*2 cm to access the board on the other end, 30 cm out to the farthest package on that board, and another 2 cm through the receiving package, for a total of about 78 cm. This large xe2x80x9ccharacteristic distancexe2x80x9d is comparable to or larger than the largest dimension of an equivalent fully two-dimensional arrangement; and this explains why no especial speed advantage is obtained in this case. Even at the speed of light, the time of flight for this distance is still several nanoseconds, which is comparable or greater than the silicon delays in current systems. But how does this compare with other potential circuit-stacking arrangements?
Of course, the most compact and basic level to begin stacking circuits would be to xe2x80x9clayerxe2x80x9d multiple integrated circuits together on the same substrate, building up circuit upon circuit with built-in interconnections between layers through vias. The characteristic distance in this case would be equal to an IC maximum dimension (perhaps 1 cm) plus several thicknesses (tens of micrometers at most), or roughly 78 times shorter than the characteristic distance of the personal-computer example. With such a tremendous comparative advantage, such an approach has been investigated and is still under investigation; this approach is inherently the most compact and probably the fastest arrangement, but is plagued by practical difficulties. For example, it is more difficult to keep such an extremely compact structure cool during operation. Also, processing problems such as perfecting planarization techniques between layers, developing re-crystallization techniques for creating quality semiconductor material for upper layers, and basic yield considerations have limited the application of this approach to stacking circuits. With the current state of the art, such truly three-dimensional integrated circuits are not practical for most applications.
The next logical level at which circuits might be stacked is at the die level; separately-manufactured integrated circuit dice might be stacked atop one another with some type of interconnection scheme linking their signals together. This approach would have a characteristic distance as small as one IC maximum dimension (1 cm) plus several wafer thicknesses (perhaps 7*0.625 mm), or roughly 54 times shorter than the personal-computer example. And in fact, an increasing interest in such an approach is becoming apparent. For example, U.S. Pat. Nos. 4,394,712 (1983) and 4,499,655 (1985) to Anthony describe a rather exotic technique for stacking silicon-on-sapphire (SOS) substrates using bored and plated holes as vias to interconnect the various circuits. Of course, such an approach is even more expensive than standard SOS chips, which are already prohibitively expensive for consumer applications. Another interesting approach is described in U.S. Pat. No. 5,019,943 (1991) to Fassbender et. al.; a stack of chips is presented wherein one edge of the chip stack assumes a xe2x80x9czig-zagxe2x80x9d shape which exposes bond pads along the edge of each chip. Electrical connections between chips are made by connecting these bond pads with bondwires. As another example, U.S. Pat. No. 5,347,428 to Carson et. al. describes a similar stack of chips, specifically memory chips, integrated with a microprocessor. Although Fassbender does not specifically mention memory chips as his primary application, his approach is also best suited for stacks of memory chips, since interconnections between chips are available along only one edge of the stack; this limits the numbers of inputs/outputs (I/Os) and is most suited to chips which are relatively large in area, but which have relatively few I/Os themselves (such as memory chips). In fact, because of the limited interconnections in these approaches, most prior-art chip-stacking schemes are not applicable to stacks of general-purpose chips which may include chips with many I/Os. Chip-stacking approaches are generally most applicable to memory chips, because the dice should ideally be the same size (width and length), and thus must usually be the same chip; in most systems, only memory chips are used in large-enough quantities to make such a stack practical. And even if all chips produced today were exactly the same size, there would still be problems interconnecting chips in a stack; consider how a pad on one corner of a chip would be connected to a pad on the opposite corner of the next-higher chip in the stack. In general, chip-stacking schemes, which normally allow only near-vertical connections between different chips, require each chip to be designed specifically for use in the stack, or else require that each chip be substantially similar to the others in the stack. Overall, chip-stacking as described in the prior art is not a viable approach to general-purpose dense circuit stacking.
The next level at which circuits might be logically stacked together would be at the package level. The addition of a package surrounding each die creates a standard size (the package size) which can be relatively independent of die size. And more I/O capability may be built into each package than is present in a chip stack. Although a stacked-package arrangement would not be as compact as true three-dimensional circuits or stacked chips, the size of a package stack would still be small enough to expect significant speed advantages. Furthermore, the interconnecting conductive traces in a package can also be designed to have less resistance and less parasitic capacitance than an integrated-circuit trace, yet be much shorter than a PC-board trace, since the density is intermediate between integrated circuit dimensions and PC-board dimensions. With packages interconnected together within the stack, most of the packages do not need to interface with a PC-board at all, new packaging technologies with smaller sizes and thus greater speeds are a possibility. As an example, packages as thin as 1 mm are already being produced, and perimeter ball-grid-array packages perhaps 1.5 times the linear dimensions of an IC die are possible. Using these dimensions, the characteristic distance of a package stack might be 1.5 cm plus 7*1 mm, or roughly 35 times shorter than the personal-computer example above. This speed is comparable to the two inherently more-compact, but less practical, approaches (true 3-d ICs and chip-level stacking) discussed above. In terms of potential performance for general-purpose circuit stacking, the package level would seem to be the most promising level to pursue. One structure for such a stackable package usable in this context is described in my prior U.S. Pat. No. 5,838,060.
Yet package stacks are not now in common use. This is due primarily to the practical concerns mentioned above with prior-art packaging technologies. Although each die need not be custom-designed for use in the stack, each package must now be designed specifically for use in the stack, with the correct connections between package internal and external contact points, and between top and bottom contacts, designed in. As mentioned previously, the costs and delays associated with designing even one such custom package are not small; the total cost and delay associated with designing and manufacturing a matched set of stacking packages for each system design is prohibitive. For example, to make a general-purpose stack comprising ten disparate dice, ten different mating packages need to be designed, and prototypes built and debugged, before the overall circuit can even be tested. And if a given chip is used in multiple designs, multiple different package designs are required for this single chip if this approach is used. Using prior-art technologies, such a stacked-package arrangement is probably only within the reach of large, vertically-integrated companies that design and manufacture chips, packages, and entire systems; and even they will not take such an approach unless the prospective market for such a system can justify such exorbitant costs in time and manpower.
Thus, there is a current need for a practical, low-cost, quick-turnaround method of producing custom interconnections in stackable semiconductor packages. Although there are few examples of such packages in the prior art, some general requirements for such an application can be determined. For example, an electrically-configurable package, quickly programmable using a low-cost programmer similar to those currently used to program EPROMs or FPGAs, would be especially well-suited for such an application. Ideally, an electrically-configurable architecture for use in this application should be compatible with a variety of packaging technologies; it would thus be desirable for such an architecture to be buildable on a variety of substrates. And, since the connectivity of the programmable architecture defines the entire circuitry of the stack, it is highly desirable, if not absolutely necessary, for the programmable elements of the architecture to maintain their states indefinitely, once programmed. Finally, it would be very desirable for such an architecture to be programmable using as few electrical contacts as possible, and preferably without requiring the programmer to contact any of the package""s internal electrical contact points.
Such a stacked packaging scheme requires a programmable interconnection architecture, for use in selectively connecting each package""s external contact points (pins, contacts, solder-bumps, etc.) and internal contact points (such as bond pads) together as needed by the system design. In such a programmable architecture, the interconnection elements are selectively programmed to connect together desired groups of conductors according to a user-defined pattern. In the prior art, such programmable architectures have been produced using a plurality of switches or other programmable interconnection elements, with one such element connected between each pair of potentially-connectable conductors. Such interconnection elements may be in the form of reprogrammable elements such as physical switches, relays, or transistors whose gates are controlled to make or break each connection. Other possible interconnection elements might be one-time-programmable (OTP) elements such as fuses or antifuses. A fuse is a programmable structure with two terminals, which initially electrically connects its two terminals together, but which, when programmed, permanently electrically disconnects them from one another. An antifuse is a programmable structure with two terminals, which initially does not electrically connect its two terminals together, but which, when programmed, permanently connects them together electrically. In general, OTP elements are cheaper to make than reprogrammable elements.
Reprogrammable elements are still preferred for many programmable interconnection applications, if the additional cost can be justified. However, for incorporation in a programmable package, such elements are not practical. Such large-scale structures as current-technology switches or relays are too cumbersome to incorporate in a compact packaging array. And transistor-based reprogrammable elements require an expensive semiconductor substrate and semiconductor processing, rather than conductive or insulating package substrates with their lower-cost package-technology processing. Also, such reprogrammable elements typically do not provide a connection that has as low a resistance as an OTP connection through a shorted fuse or antifuse of comparable size. Furthermore, such reprogrammable elements generally require considerable additional controlling logic and circuitry, which again adds to the size, cost and power requirements of any design. Thus, an electrically-programmable interconnection architecture suitable for incorporation into configurable, stackable IC packages should ideally be based on OTP interconnection elements such as fuses and antifuses.
In the prior art, programmable interconnection architectures using fuse and antifuse elements have been proposed in many different configurations, each with different advantages and disadvantages. Many approaches combine the OTP elements with reprogrammable elements such as transistors; of course, such approaches are inappropriate here, since again a semiconductor substrate would be required.
Programmable interconnection architectures using only fuses might be constructed; however, such arrays of fuses have practical limitations. For example, a fuse-based interconnection network presents a plurality of conductors initially connected together by fuses. Unwanted connections are then disconnected by programming the unwanted fuses to the open state. Without the assistance of reprogrammable elements, it becomes difficult to isolate the desired fuse from all others for programming, because of possible current paths in parallel with the desired fuse. Depending on the network configuration, these xe2x80x9csneakxe2x80x9d paths can demand large currents to be supplied, above the current needed to actually program the desired fuse. With more complicated networks, keeping track of and accounting for all possible sneak paths can become impractical or impossible. In short, although fuse elements have very desirable electrical characteristics, programming a complicated network based entirely on fuses can be prohibitively complex and time-consuming, if it can be reliably performed at all.
By contrast, an antifuse-based interconnection architecture initially presents a plurality of unconnected conductors, which are subsequently programmed by shorting the desired antifuse to the shorted state. This is a much simpler situation that in the above-mentioned fuse-based interconnection architecture. However, care must still be exercised during programming to ensure that excessive voltages do not appear at the terminals of antifuses which are not to be programmed, inadvertently damaging or programming them. More problematically, undesired and unprogrammed antifuses are still present after programming, and must be protected from such accidental programming during the entire operating life of the network.
One very promising architecture is proposed in U.S. Pat. No. 5,321,322 to Verheyen et. al., in which a combination of fuses, antifuses, and tri-state elements electrically equivalent to series-connected fuse/antifuse pairs, is used. The described architecture essentially uses a fuse and antifuse in series as the primary programmable OTP element in the interconnection architecture; this eliminates the problems associated with fuse-only or antifuse-only architectures. Also, Verheyen describes an architecture which might be built on a variety of substrates, so that it might be suitable for a stacked-package scheme.
The particular architecture described by Verheyen, however, allows a user to connect together selected ones of an undifferentiated xe2x80x9cplurality of input/output pads through which programming signals may be transmitted to the interconnect architecturexe2x80x9d, in essence requiring any or all of the I/O pads to be available for transmitting programming signals; thus all of the I/O pads must be electrically accessible to the programmer during programming. However, such an architecture is not practical for use in a programmable package. An architecture used to make an IC package programmable inherently has two main types of I/O pads: 1) package xe2x80x9cexternal contact pointsxe2x80x9d physically located on an exterior surface of the package, and used to connect the package to outside circuitry (e.g. pins, solder-bumps, etc.), and 2) package xe2x80x9cinternal contact pointsxe2x80x9d physically located inside the package, and used to connect to structures inside the package, such as an included IC die (e.g. bond pads, pads that mate with flip-chip solder bumps, etc.). In other words, package internal contact points, which are typically too small to be easily contacted even if they are accessible, form a substantial subset of said architecture I/O pads; contacting all architecture I/O pads would require both a means of contacting the package external contact points and a probe card or other means of simultaneously contacting the tightly-spaced package internal contact points during programming, in some cases, it may be essentially impossible to physically contact the package internal contact points during programming, especially if the package is to be programmed after the die has been inserted and the package has been hermetically sealed. And additional conductors, routing a connection from each internal contact point out to the package surface, are redundant after programming, add unwanted complexity to the package, and degrade performance of the programmed package. Therefore, a Verheyen architecture, included within a programmable package, is unduly difficult or impossible to program, and may degrade package performance.
Also, the Verlieyen architecture provides for general user-selected interconnection of said I/O pads without any differentiation between them; such an architecture is considerably more flexible than what is required for a configurable package, and thus must provide far more programmable elements than are really required to interconnect an array of stacked packages. For example, internal contact points (that are used to contact an included IC die) will rarely need to be connected together; so if a Verheyen architecture is used in a programmable package, almost all of the programmable elements included to allow connections amongst internal contact points are wasted. Similarly, by far the most common connections actually needed between external contact points in a stacked-package interconnect scheme will be between associated bottom-side contacts and top-side contacts (where nets pass vertically through the package stack through a series of such connections); other connections amongst package external contact points will likewise be rare. So again, most of the programmable elements provided within a packaged Verheyen architecture to allow connections amongst external contact points would be wasted. So even if a practical way of programming a Verheyen architecture within a stackable package was found, it would in general still have far more programmable elements than are required for this application; of course, this leads to higher cost, lower performance and lower yield.
Basically, the Verheyen patent describes an architecture which is quite suitable and desirable for a flexible, multi-purpose 2-dimensional interconnection network, where any given signal might enter the architecture through any pad (making any pad potentially an input) and exit via any other pad (making any pad also potentially an output); such a situation requires that any two terminals of the interconnection architecture be connectable. But such general-purpose architectures are not well-suited for the more limited requirements of a programmable-package interconnection scheme.
However, starting with such a flexible, general-purpose architecture, one can list the modifications which are of obvious value in transforming it to a form more appropriate for a programmable package. These changes can be enumerated as the purposes and requirements of the two applications are compared.
As stated before, the basic purpose of the general-purpose architecture is to connect each signal arriving at any one of its undifferentiated external I/O pads to any other one (or more) of its undifferentiated external I/O pads; whereas the primary purpose of a programmable-package architecture is to xe2x80x9cbring outxe2x80x9d the IC signals, i.e. to connect each package internal contact point to one (or more) of the package external contact points (and of course, in a stackable package, some connections between the external contact points, particularly related top- and bottom-contacts, are also required). In essence, the conversion to an idealized programmable package architecture requires that a large number of Verheyen I/O pads be xe2x80x9cmovedxe2x80x9d from the package exterior to the interior, where they become essentially inaccessible during programming (ideally, no contact with these pads should be required, and it should not be required that any programming signals be sent through these pads). Thus in a programmable package, there is a clear, basic difference between those I/O pads formed by internal contact points and those formed by external contact points. Verheyen""s undifferentiated xe2x80x9cplurality of I/O pads through which programming signals may be transmitted to the interconnect architecturexe2x80x9d must therefore be differentiated into a first plurality of I/O pads which ARE accessible for programming (package external contact points), and a second plurality of I/O pads which ARE NOT accessible for programming (package internal contact points). It is therefore a goal of the present invention to provide such a programmable architecture, where programming is performed by applying programming signals only to a predetermined subset of the I/O pads of the architecture.
Secondly, the basic requirement of a flexible general-purpose architecture is that any two groups of I/O pads should be connectable by the architecture; whereas a programmable-package architecture requires such maximum flexibility only in the connections between the now-differentiated first and second pluralities of I/O pads; only rare connections within each group are required (again with the exception of the frequent connections required between related top- and bottom-contacts if the package is stackable). Ideally, a programmable architecture for use in programmable-package scheme should take advantage of these inherent differences between the two pluralities of pads, limiting the number of interconnection elements provided for rarely-used connections. It is therefore a goal of the present invention to provide a programmable architecture which is efficient in meeting the needs of a programmable IC package, providing interconnection elements in proportion to the requirements of this particular application.
Thirdly, even if a Verheyen architecture was built into a stackable package in particular, this general-purpose architecture would presumably provide connections between the various undifferentiated I/O pads, including connections between associated top- and bottom-pads, which would generally be of only average length and electrical properties; however, since nets may contain several of these connections in series, an architecture designed for stackable packages should ideally provide a separate means for making these important connections with superior electrical properties. Thus, it is a goal of the present invention to provide an architecture for use in stacked, configurable packages which provides particularly short, high-performance connections between associated bottom-side contacts and top-side contacts.
With these desired modifications clearly in mind, it is useful to consider further how such a programmable-package architecture might be built, and particularly how it might be programmed without physical access to its second plurality of I/O pads.
One means of configuring such a programmable fuse/antifuse architecture (without physical contact to all architecture I/O pads or terminals during programming) might include a means for electrically connecting a control terminal X to one of a plurality of architecture terminals, some of which may be otherwise inaccessible during programming (such as the package internal contact points). This is how programmable fuse/antifuse architectures which include reprogrammable elements are generally programmedxe2x80x94the connections to the architecture terminals during programming are controlled by the reprogrammable elements, such as logic-controlled transistors, within the architecture. However, without reprogrammable elements, this task becomes much more difficult.
Even more useful would be a building block which allowed a user to connect a control terminal X to each of the plurality of controlled terminals, at different times. As an example, consider the special case where control terminal X must be connected sequentially to the first, second, . . . Nth of N controlled terminals, in order that some electrical operation might be accomplished in each of these configurations. This usage is often encountered when encoding information into any machine, and is therefore of general utility. More specifically, this defines a particularly useful special case of the required architectural building block. This form in particular might find general utility in the programming of fuse/antifuse interconnection architectures, where programming is often based on sequencing through various architecture terminals. It is therefore a goal of the present invention to provide such an architectural building block, whereby the interconnection elements may be selectively programmed to connect control terminal X to each of a group of controlled terminals in a particular sequence, without requiring previous electrical connections between control terminal X and these controlled terminals.
Also, it would be advantageous if each such connection itself could be temporary, used only during programming at a specific step in the programming sequence. It is therefore a goal of the present invention to provide the aforementioned architectural building block, wherein means are further provided to allow control terminal X to be subsequently disconnected from each controlled terminal.
One patent in the prior art describes a structure with capabilities somewhat similar to those required. U.S. Pat. No. 5,321,322 to Whitten et. al. discusses a deactivatable, reactivatable, ESD (electrostatic discharge) protection device for preventing damage to an electrical component; the structure described therein is a fuse/antifuse building block capable of disconnecting a pair of initially-connected terminals and then reconnecting/redisconnecting them up to three more times. However, as disclosed in that patent, the Whitten structure does not connect a control terminal to each of several controlled terminals in a sequence; instead, it is intended to connect (and disconnect) a control terminal to/from another single terminal, several times. Also, it is not intended to assist in the programming of any interconnect architecture (beyond protecting it from ESD damage). Further, the Whitten structure is not intended for use in a stackable, configurable package. And, in any case, it provides only a few steps of disconnection/reconnection; certainly not enough to help much in programming any real-world stacked-package system including perhaps hundreds of internal contact points and hundreds or thousands of external contact points in each package.
Accordingly, several objects and advantages of the present invention are:
1. To provide a means for sequentially connecting a control terminal to each of a plurality of controlled terminals, using a fuse/antifuse architecture to reduce manufacturing costs compared to IC (transistor-based) interconnection architectures.
2. To provide a means for sequentially connecting a control terminal to each of a plurality of controlled terminals through a low-impedance path.
3. To provide a means for sequentially connecting a control terminal to each of a plurality of controlled terminals which does not require active devices or active control signals.
4. To provide a means for sequentially connecting a control terminal to each of a plurality of controlled terminals using a fuse/antifuse architecture, which does not require any preexisting electrical connection to these terminals to assist in programming.
5. To provide a means for sequentially connecting a control terminal to each of a plurality of controlled terminals, individually.
6. To provide a user-programmable interconnection architecture, suitable for incorporation into IC packages, which does not require a semiconductor substrate or transistors, and therefore may be built for a relatively low cost.
7. To provide a user-programmable interconnection architecture, suitable for incorporation into IC packages, which, once programmed, retains its state indefinitely.
8. To provide an user-programmable interconnection architecture which may be integrated into an IC package in such a manner that the interconnection architecture may be completely programmed by the application of currents and voltages only to contact points on the exterior of the package, without requiring application of currents and voltages to the internal contact points of the package.
9. To provide an user-programmable interconnection architecture for integration into an IC package which efficiently provides configurability in the package connections, by providing substantial flexibility in the connections between the package internal contact points and external contact points, but only limited flexibility in connections amongst the package internal and external contact points.
10. To provide a user-programmable interconnection architecture for integration into a stackable IC package that makes specific provision for programmably connecting corresponding bottom-surface and top-surface package external contacts together, selectively creating short, high-performance connection paths through each package.
11. To provide a means whereby IC packages may be quickly and economically customized in their electrical connections.
12. To provide a quick-turnaround, electrically-programmable means whereby ICs may be combined into a system with customized connections.
13. To provide a new means whereby systems can be quickly and economically modified in their connections, resulting in quicker debugging and faster time-to-market for systems manufacturers.
14. To provide a practical, low-cost, quick-turnaround method whereby slacked circuits may be connected together in a compact, high-speed assembly with significantly-reduced characteristic distances compared to prior art methods.
According to a first aspect of the present invention, a first architectural building block described as a xe2x80x9csingle ladder networkxe2x80x9d is presented, comprising a plurality of first antifuse elements each having first and second terminals, a plurality of first fuse elements each having first and second terminals, a first plurality of control terminals including at least a xe2x80x9cgroundxe2x80x9d terminal and a xe2x80x9cmasterxe2x80x9d terminal, and a second plurality of xe2x80x9crungxe2x80x9d or xe2x80x9cslavexe2x80x9d terminals. In this, the single ladder""s simplest form, the antifuse elements are connected together in series, with the second terminal of each antifuse connected to the first terminal of the next antifuse, forming a chain of antifuses with a first chain end comprising the first terminal of a first antifuse, and a second chain end comprising the second terminal of a last antifuse. The first chain end is directly connected to the master terminal, and may thus be considered as forming a xe2x80x9cbonusxe2x80x9d slave terminal. Each second antifuse terminal is connected to a different one of the slave terminals, and is further connected to the second terminal of a different one of the fuse elements; each first fuse terminal of each fuse element is electrically connected to the ground terminal. Thus, in this most basic form, the single ladder network is composed of an array of xe2x80x9crungsxe2x80x9d connected in series, wherein each rung comprises one antifuse element, one fuse and one slave or rung terminal; it is a xe2x80x9csinglexe2x80x9d ladder because each rung has only a single antifuse. In this simplest form, it is necessary to provide some means of shorting the master terminal to the ground terminal prior to programming, in order to prevent premature inadvertent programming due to an ESD event. The simple addition of another fuse element, connected between the master terminal and the ground terminal, provides protection against such ESD damage; with this addition, the single ladder becomes an xe2x80x9cESD-protected single ladderxe2x80x9d.
In the ESD-protected single ladder network, the antifuses both isolate the slave terminals from each other initially and provide a means of subsequently connecting them together. Since the master terminal and the slave terminals are all initially connected to said ground terminal, each through an unblown fuse, all antifuses in the ladder network are initially protected against premature undesired programming. If suitable electrical programming signals are applied to the master and ground terminals, the master terminal may be repeatedly disconnected from the ground terminal (by blowing the next fuse), then reconnected and simultaneously connected to the next rung terminal of the ladder (by shorting the next antifuse). No programming signals need be applied to the rung terminals to achieve this functionality. The ground terminal remains connected throughout the programming sequence with all rung terminals which have not yet been connected to the master terminal, thereby protecting all remaining unprogrammed antifuses from accidental programming until their turn arises in the programming sequence. In these simplest forms of the ladder network, the master terminal remains connected permanently to each rung terminal, once connected; however, often it would be advantageous to provide a means of breaking these connections after they are used, so that the master terminal is only connected to one rung terminal at a time.
Therefore, according to a second aspect of the present invention, a second architectural building block described as a xe2x80x9csegmented ladderxe2x80x9d network is presented, comprising a single ladder of the present invention, a plurality of second conductors, and a plurality of third fuse elements. Said third fuse elements split each second conductor into two initially-connected proximal and distal xe2x80x9csegmentsxe2x80x9d, wherein each proximal segment is connected directly to a different one of the slave terminals; these segments may subsequently be separated by blowing said third fuse. This structure allows each second conductor distal segment to be connected to the ladder""s master terminal through its slave terminal and proximal segment, and subsequently disconnected by blowing its third fuse. Of course, in the limiting case wherein each said proximal segment is of zero length, this structure reduces to a plurality of second conductors, each connected to a different slave terminal through a different third fuse; this simpler case will be assumed in many of the following examples, for ease of discussion.
Since a connection to each terminal of a fuse is needed to blow the fuse, a separate electrical connection to each second conductor distal segment is required to blow its third fuse; this connection will normally be provided by xe2x80x9csegmentation assistxe2x80x9d rails with programmable three-state elements linked to each distal segment, so that temporary connections to each distal segment can be made. Thus, said segmentation assist rails provide means whereby said third fuses may be programmed.
According to a third aspect of the present invention, a third architectural building block described as a xe2x80x9cdouble ladderxe2x80x9d network is presented, comprising a plurality of first antifuse elements and a plurality of first fuse elements, connected together and further connected to a first xe2x80x9cgroundxe2x80x9d terminal and a plurality of slave terminals. This double-ladder network is identical in structure to the single ladder, except that the chain of single antifuses becomes a chain of series-connected pairs of antifuses. The functionality is likewise identical, except that the antifuse-programming procedure must now be replaced by an antifuse-pair programming procedure, including a step requiring twice the Vpp voltage of a single antifuse programming procedure. In essence, this is the same structure as the single ladder; however, this building block has the important property that no programming signal required by any single ladder network (built in the same antifuse technology) will program one of the antifuse pairs. This allows a double ladder to be used to combine a plurality of single ladder networks into a larger hierarchical ladder network, with a greater total number of slave terminals. This aspect of the present invention effectively increases the total possible number of slave terminals which may be sequentially connected to the master terminal, with better electrical performance than an equivalent single ladder network.
According to a fourth aspect of the present invention, a fourth architectural building block described as an xe2x80x9cassisted double-ladderxe2x80x9d network is presented. Said assisted double ladder comprises a double-ladder, and further comprises a third xe2x80x9cintermediate assistxe2x80x9d ladder control terminal, and a plurality of second fuse elements. Said intermediate assist terminal is connected through one of said second fuse elements to each intermediate antifuse terminal connection which links each pair of antifuses. This form of the double ladder provides ease in programming the ladder, since each antifuse can again be programmed individually, using the third assist terminal to transmit further programming signals. Also, this structure has a reduced likelihood of errors before or during programming, since the voltage of the intermediate antifuse terminal connection within each antifuse pair is no longer floating before or during programming (as it is in the basic double ladder). Further, this assisted double-ladder network can be generalized into a means for connecting ladders together according to an hierarchical scheme with an arbitrary number of hierarchy levels, so that ladders with a very-large number of slave terminals can be provided, with significantly-improved performance compared to a single ladder network with the same number of slave terminals.
According to a fifth aspect of the present invention, a programmable surface acoustic wave (SAW) interdigital transducer is presented which incorporates a segmented ladder network to produce a new type of transducer, in which each interdigital finger may be programmably connected to either the positive or negative terminal of said transducer.
An IC package has electrical contacts, such as pins or solder-bumps, located on the exterior of the package (xe2x80x9cexternal contact pointsxe2x80x9d) and electrical contacts for the IC die, such as bond pads, located inside the package (xe2x80x9cinternal contact pointsxe2x80x9d). It is useful to be able to configure the connections between these internal and external contact points using a programmable interconnect matrix linking these internal and external contact points. However, it is preferable to be able to program each package using the application of electrical signals only to the external contact points of the package; then programming can be achieved using a socketed programmer which contacts only the external package pins or contacts, much as EPROMs are programmed. In essence, this requires that programming of the interconnect matrix be conducted even though some of the matrix rows or columns are not directly accessible during programming.
Therefore, according to a sixth aspect of the present invention, a user-programmable interconnect architecture is presented, useful for integration into configurable integrated circuit (IC) packages. This architecture incorporates the ladder network of the present invention to allow a user to selectively connect inaccessible internal contact points to the external contact points, without requiring contact to these inaccessible contact points during programming. For example, using the architecture of the present invention, a user can selectively connect package internal contact points (such as those tiny internal contact points which are commonly used to connect to an included semiconductor die through bond wires or other electrical means), to selected external contact points in a predetermined pattern, without opening the package and contacting these internal contact points with a probe card or other means. This allows a user to programmably and flexibly connect these package internal contact points to the package external contact points in a user-defined pattern, by applying electrical programming signals only to the package external contact points.
If the configurable package is also stackable, it has additional requirements. A stackable IC package has external contact points situated on the top surface of the package (xe2x80x9ctop contactsxe2x80x9d), and matching external contact points on the bottom surface of the package (xe2x80x9cbottom contactsxe2x80x9d), where at least some of these top contacts are individually associated with a corresponding bottom contact. Within a stackable, programmable package interconnect scheme, it is particularly useful to be able to make or break high-performance connections between the associated pairs of top and bottom contacts, in addition to the configurable connections between these external contact points and the package internal contact points.
Therefore, according to a seventh aspect of the present invention, a fifth architectural building block described as a xe2x80x9cprogrammable contact structurexe2x80x9d is provided, ideal for incorporation into configurable, stackable IC packages, wherein a selected pair of package external contact points, including one top contact and one bottom contact, is associated with a common xe2x80x9cinternal contact terminalxe2x80x9d located within the package. This internal contact terminal may in turn be a terminal of a programmable interconnect matrix within the package, allowing configurable connections to other conductors within the package. The programmable contact structure of the present invention also allows a user to selectively make permanent electrical connections between its three terminals: thus signals connected to its top or bottom contact may be routed to its internal terminal; or signals which must pass vertically through the package may be routed by simply connecting the top and bottom terminals together.
According to an eighth aspect of the present invention, a complete stacking architecture, incorporating both the programmable external contact structure and the ladder network of the present invention, is also presented. This complete architecture allows a user to selectively connect inaccessible package contact points to the internal contact terminals associated with the various top and bottom external contact points, without requiring direct access to these inaccessible contact points during programming. For example, using this complete stacking architecture of the present invention, a user can selectively connect package internal contact points (such as those tiny internal contact points which are commonly used to connect to an included semiconductor die through bond wires or other electrical means), to selected internal contact terminals in a predetermined pattern, without opening the package and contacting these internal contact points directly with a probe card or other means. This allows a user to programmably and flexibly connect these package internal contact points to the package external contact points (top and bottom external contacts) in a user-defined pattern, using the application of electrical programming signals to only the package external contact points.
Further, in some cases it may even be desirable to program such a configurable, stackable, IC package after the IC die is already inserted into the package. However, if prior-art programmable fuse/antifuse interconnect matrices are used to make configurable packages for standard ICs, such an approach is generally precluded because the signals used to program the matrix can damage the inserted IC die.
Therefore, according to a ninth aspect of the present invention, an optional sixth architectural building block is presented, described as a xe2x80x9cdie isolation structurexe2x80x9d, which provides a means for isolating each package internal contact point from its associated die-attach contact point (such as a bond pad) so that the potentially-damaging signals present during programming are not applied to the die-attach contact points.
Using the programmable architecture of the present invention to connect such internal contact points to internal contact terminals in a predetermined pattern, and using the programmable contact structures to further connect these internal contact terminals to desired top and bottom external contacts, a user can select the desired connectivity between internal and external contact points. Further, such stackable packages may also be programmed with a user-defined connectivity between associated top and bottom contacts. Then, when such programmed packages are subsequently stacked together, an overall circuit may be created, without an additional two-dimensional interconnecting substrate, by the total user-defined connectivity of all included programmed packages in the stack.
When a vertical stack of programmed packages using this architecture is finally connected together to complete such a circuit system, xe2x80x9ctree-likexe2x80x9d nets are formed, making the connections between included IC dice. Each net has a xe2x80x9croot-likexe2x80x9d connection that runs horizontally through the lowest package included in the net; it connects a specified internal contact point, connected to an IC die terminal, to a predetermined top external contact on this package. Each net runs, trunk-like, vertically to the uppermost package needed to complete this net, through all intervening packages via xe2x80x9ctrunk connectionsxe2x80x9d (connected top/bottom contacts of selected contact structures); each top contact in the net is connected to the corresponding bottom contact on the next-higher package in the stack. In each package which has an internal contact point (and its connected die terminal) that is included in this net, a further xe2x80x9cbranchxe2x80x9d connection runs horizontally through the package from the trunk to the internal contact point. In the uppermost package included in the net, the xe2x80x9ctop branchxe2x80x9d connects an internal contact point only to a bottom contact, with no trunk connection. With this architectural arrangement, multiple unrelated xe2x80x9ctreesxe2x80x9d can be placed atop one another in the same trunk position, providing more routability than would otherwise be available.